1. Technical Field
The present invention relates to fabrication of semiconductor devices and more particularly, to methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer.
2. Discussion of the Related Art
With the improvement of high integration of semiconductor devices and the design trend of a low-power consumption thereof, length of the gate of a transistor is reduced, and operation voltage is also reduced. With the reduction of a design rule for high integration of a semiconductor device, since a parasitic capacitance is increased and a short channel effect occurs, speed of the device is reduced. Furthermore, with the narrowness of widths of a gate and source/drain regions, silicide is difficult to form, and thus, a high-performance transistor is difficult to provide.
For example, as shown in FIG. 1, a semiconductor device with a conventional technology includes a gate insulating layer 11 formed on a semiconductor substrate 10, a gate 12, and source/drain regions 14 formed inside the semiconductor substrate 10 at both ends of the gate 12. Insulating layer spacers 13 are formed on the sidewalls of the gate insulating layer 11 and the gate 12. The gate 12 and the source/drain regions 14 are covered with silicide layers 15a, 15b to reduce contact resistance.
Since the size of the gate 12 is reduced with the improvement of high integration of a semiconductor device, a doping concentration of the source/drain regions 14 is increased in order to suppress the generation of a short channel effect. However, if the doping concentration is increased, an overlap width W1 of the gate 12 and the source/drain regions 14 is increased, and an overlap capacitance (Cov) between the gate and the source/drain regions, as one of parasitic capacitances, is increased. Due to the parasitic capacitance, a speed of the device, which is composed of millions of transistors, is reduced, and thus, power consumption is increased.
A structure of a T-shaped gate to reduce contact resistance is disclosed in U.S. Pat. No. 4,599,790, entitled, “Process for forming a T-shaped gate”, issued to Kim, et. al.
Referring to FIG. 2, a T-shaped gate 21 is composed of an upper region 21a having a relatively large width, and a lower region 21b being relatively narrow in width. That is, a width W2 of an upper region 21a as a silicide formation region is maintained, and an overlap area between the T-shaped gate 21 formed on the semiconductor substrate 20 and the source/drain regions 22 formed inside the semiconductor substrate 20 can be reduced. Thus, with the presence of the T-shaped gate 21, the reduction of speed of a device due to the parasitic capacitance can be prevented.
In order to solve the problem that hot carriers are injected into a gate insulating layer by the short channel effect, a lightly doped drain (LDD) structure has been introduced. As one of the methods of forming such an LDD structure, L-shaped spacers are formed on the sidewalls of a gate, and low concentration source/drain regions and high concentration source/drain regions are formed using the gate and the L-shaped spacers as ion implantation masks.
FIG. 3 is a sectional view schematically illustrating a structure of a semiconductor device having a conventional L-shaped spacer, which is disclosed in U.S. Pat. No. 6,087,234, entitled, “Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction,” issued to Shye-Lin Wu, et. al.
As shown in FIG. 3, a semiconductor device having a conventional L-shaped spacer includes L-shaped spacers 33 covering the sidewalls of a gate insulating layer 31 and a gate 32, and a semiconductor substrate 30 around them. Low concentration source/drain regions 34a are formed inside the semiconductor substrate 30, overlapping the L-shaped spacer 33, and high concentration source/drain regions 34b are formed overlapping the low concentration source/drain regions 34a. 
In the semiconductor device having a typical spacer as shown in FIG. 1, if an interval between the neighboring gates 12 becomes too small, it is difficult to deposit a metal layer between the spacers 13 covering the sidewalls of the gate. Thus, with the increased integration of the device, it is difficult to form a silicide layer 15b in the source/drain regions 14. On the contrary, in the semiconductor device as shown in FIG. 3, a metal layer can be readily deposited even on the semiconductor substrate adjacent to the L-shaped spacer 33, so as to provide a sufficient area for the silicide layer 35b covering the source/drain regions 34.
As such, the semiconductor device having the T-shaped gate can have a sufficient enough area of the gate silicide layer, and can reduce an overlap area of the gate and the source/drain regions. Further, the semiconductor device having the L-shaped spacer can have a sufficient enough area of the silicide layer covering the source/drain regions. However, it is not easy to form the L-shaped spacer on the sidewalls of the gate because of the structural characteristics of the T-shaped gate. Therefore, it is necessary to provide a method of easily fabricating the semiconductor device having the L-shaped spacer on the sidewalls of the T-shaped gate.